Design and Implementation of Output Buffer in a 14nm CMOS

doi:10.21203/rs.3.rs-7007565/v1

This work presents the design and implementation of a single-ended (SE) transmitter (TX) as part of a high-speed input/output (HSIO) interface, developed using 14nm FinFET technology. The proposed transmitter is integrated into a wire bond packagefor FPGA systems, addressing a range of design challenges across multiple stages of development. It supports multiple I/O standards and operates reliably at frequencies up to 533 MHz, making it well-suited for memory interface applications. To enable compatibility with diverse system requirements, the design employs thick-oxide transistors, supporting I/O supply voltages from 1.2V to 1.8V. Special attention is given to robustness, with the driver exhibiting low sensitivity to process, voltage, and temperature (PVT) variations, and maintaining a near-linear output resistancewith only ±15% variation across the output voltage range. Additionally, the transmitter features programmable output and input impedance, configurable from 25Ω to 50Ω for transmit and 50Ω to 100Ω for receive paths, enabling effective transmission line impedance matching.

Binary weighted driver

Dynamic ODT

DDR

Impedance calibration

Linear weighted driver

Parallel termination

Series termination

Static thermometer coded driver

For the past 60 years, the semiconductor industry has adhered to Moore's Law, which predicts the doubling of transistor count in an IC every two years. This consistent scaling has resulted in smaller, faster, and more cost efficient transistors to meet growing consumer demands [1]. By scaling the devices down it is implied that there is reduction in the threshold voltage of the transistors as there is transition from one technology node to the next and bringing the core voltage supply down which facilitates construction of IPs delivering high speed, low power and small area. While the core devices have been scaling down aggressively the external world devices functioning at higher voltage supplies are still to be supported [2]. There is a corresponding demand for processing electrical signals at increasingly higher rates. FPGAs features unique programmable IO structures which enables them to communicate with a very wide variety of other devices. For a single set of physical IOs to programmable support distinct IO interfaces and standards is challenging, as it requires adaptation to different voltage levels, electrical characteristics, timing specifications, and command protocols [3]. Proposed IO single ended transmitter (Tx) can overcome the above mentioned challenges. The remaining part of this paper is structured as follows: Section II presents an overview of the IO buffer. Section III summarizes the simulation results for the transmitter, while Section IV concludes the paper with discussions and conclusions.

Employing terminated transmission lines as an interconnection method offers numerous system-level benefits compared to driving capacitive loads. The wire behaves as a resistive load on the output pad, enabling the signal rise time at the pad controlled by the speed of the internal transistor drive, rather than the RC time constant of the output transistor resistance and the external capacitive load. Additionally, the rise time at the output pad is transmitted to the receiving end without distortion. he use of series termination in driving transmission lines is a widely recognized technique, Fig. 1, that positions the line termination at the driving end rather than at the receiving end. This approach involves placing a series resistor, matching the line impedance, in line with the voltage source driver. With an infinite line, the line can be modeled as a resistance equivalent to its impedance connected to a voltage source equal to the idle state of the line. Together, the termination resistor and the equivalent line resistance create a voltage divider with an initial step waveform 1 resulting in a forward-propagating voltage step waveform 2 with an amplitude equal to half the driver voltage swing. With a finite line, this half-amplitude forward-propagating wave reflects entirely, producing waveform 3, upon reaching the open, unterminated end of the line. Resulting in a backward-propagating wave with half-amplitude, traveling back toward the driver.

At the unterminated end of the line, the superposition of the forward and reflected backward waves creates a full-amplitude logic swing at that specific point on the line. When the backward-propagating wave reaches the driver, it is completely absorbed. At the driving end of the transmission line, the waveform forms a stair-step, remaining at the half-amplitude for the round-trip delay of the transmission line. Power is dissipated in the termination resistors solely during the round-trip delay on the line. In a static state, no power is consumed, and no current flows because there is no voltage drop across the resistor. The waveform on the transmission line accurately mirrors the driver waveform only at the end of the transmission line, making this termination approach suitable primarily for point-to-point communication [4]. Matching the output impedance of a signal driver to the characteristic impedance of the transmission line it drives, is crucial for preventing signal reflections caused by voltage level transitions at the pad. This matching helps to avoid unwanted signal degradation, ensuring reliable signal transmission. Impedance matching poses several challenges. First, the process variations inherent in integrated circuit manufacturing, such as the transistor implanting doping levels, effective channel lengths of MOSFET’s, gate oxide thickness, and diffusion resistance, can cause the output impedance of two supposedly identical circuits to differ. In particular, variations in any or all of the above process parameters can result different integrated circuits intended to perform the same function to be categorized as slow, nominal, or fast. In other words, two seemingly identical integrated circuits can differ in any or all of the process parameters. When the parameters approach the fast case, the resistance of various components within the chip decreases. Conversely, as the parameters deviate further and further from the ideal case, performance of the chip deteriorates, and particularly the resistance of the chip's components increases, which is referred to as the slow case. Furthermore, variations in voltage and temperature can lead to variations in the output impedance of a given chip. For instance, the driver output impedance can differ noticeably between variations in the operating voltage, even within a small operating voltage tolerance range. Additionally, as the integrated circuit nears its maximum operating temperature, the resistance of the integrated circuit components increases. To address these challenges, variable impedance output drivers have been developed to enable adjustments to the driver output impedance due to manufacturing process, voltage, and temperature (PVT) variations.

Controlled impedance CMOS output drivers can be either current controlled or voltage controlled. Current controlled drivers employ analog voltages to control gate voltages which in turn controls the FET operating current, and thus resistance, of an output driver. Voltage controlled drivers use discrete logic levels to turn combinations of driver FETs on and off. By using various combinations of operating driver FETs, effective FET width is controlled and thus the FET resistance is programmable. Current, or analog, controlled drivers are sensitive to noise. Voltage controlled, or digitally controlled, output drivers offer higher noise immunity due to their discrete operating nature and as such their calibration schemes are easier to implement and manage [5]. The focus of this paper will center on voltage controlled output drivers.

An output driver unit can be implemented using a simple driver, as depicted in Fig. 2 (a). However, such drivers exhibit nonlinear behavior, due to transistor characteristics, throughout their operating range. As the g_m (transconductance) of the transistor varies with the output voltage. In high-speed communication systems, transmit termination is essential to prevent signal reflection issues. Thus, a driver unit with a linear response across its entire operating range is preferred. The basic structure of a Source Series Termination (SST) output driver unit, shown in Fig. 2 (b), addresses this need. The term source in SST highlights the fact that the transmitter can be considered as self-terminated to fully absorb any reflected signals from the receiving end [6]. The output stage of the driver unit is subdivided into pull-up and pull-down branches, consisting of PMOS or NMOS switch transistors followed by series termination resistors R. In SST, a series resistor is used to improve impedance linearity and to minimize the range of impedance variation of the output buffer across simulation corners. Each branch is impedance matched to the transmission line impedance. In contrast to the traditional SST driver topology, which incorporates two resistors, our design employs a single series resistor between the transistors and PAD in Fig. 2 (c). This configuration cuts the parasitic capacitance associated with the resistor by making the number of the resistors half. The node where the resistor is connected to the driver is always driven either by NMOS or PMOS, reducing the node’s charging and discharging time [7].

The sum of the impedance of the driver's transistor and series resistor is equal to the line impedance. Increasing the percentage impedance proportion of the series resistor relative to the transistors from 50%, 75% to 90%, the output impedance response flattens, but at the cost of dramatically increasing the output capacitance. The series resistor is sized to yield about 85% of the overall impedance and this can limit the non linearity of the driver to less than 15% over its full range.

An optimal value of the resistance 1.8 KΩ is chosen depending on area constraints versus the linearity desired. The PAD terminal is usually connected to the transmission line of impedance assuming Z₀ and it is crucial that the impedance offered by the driver output matches with Z₀ (impedance matching) to reduce the effects of unsettled signal ringing due to reflections. Since the transmission line impedance and driver impedance act as potential dividers, the voltage at the PAD will be half the IO supply . The number of fins, fingers and widths of the PMOS and NMOS are decided based on DC simulations by connecting PAD to a voltage sources of and turning one of the two transistors on. Measure the current through the PAD and using ohm law find the output impedance. The experiment is repeated for deciding the size of the other transistor. The width of the FETs is fixed based on which value of the widths gives the appropriate impedance matching Z₀ at the output at the nominal condition.

Variable impedance output drivers often employ a pure thermometer code for PVT impedance matching control to limit the change in output impedance when the PVT control code is updated. Specifically, the impedance networks utilize a thermometer code where a nth-order signal W_n is activated (set to 1) all of the lower-order signals W₁ to W_n-1 are also activated. In such a circuit, a first FET leg is activated and then each subsequent FET leg is activated until the desired output impedance is achieved. Consequently, at least one leg remains active at all times to ensure that during the switching of FET legs on or off, the FET legs are never switched from all off to all on or vice versa, which would result in a spike in the output impedance. Table I presents a pure 6-bit thermometer code, where each bit from 0 to 5 in the code word W corresponds to a 20% incremental step in admittance (Y).

TABLE I 6-bit thermometer code

W₅	W₄	W₃	W₂	W₁	W₀	Y= 1/Z	Z
0	0	0	0	0	1	1	1
0	0	0	0	1	1	1+0.2	0.833
0	0	0	1	1	1	1+0.4	0.714
0	0	1	1	1	1	1+0.6	0.625
0	1	1	1	1	1	1+0.8	0.555
1	1	1	1	1	1	1+1	0.5

The controllable range of sensitivity of output impedance is limited between 1 and 0.5, as illustrated in the thermometer code table I example. The admittance is incremented by 0.2 or 20% for each step, which require one bit in thermometer code for each step. So, one of the disadvantage of a pure thermometer code is the substantial number of bits and therefore control lines needed to support a wide range of output impedance. As the required step sensitivity increases, the number of control lines grows exponentially. For instance, if the goal is to adjust the admittance by just 1% to enhance the sensitivity of each step, the PVT control circuit would need 101 control lines – twenty times the number of lines required to adjust it to the 20% increments. Alternatively, to expand the adjustable output impedance range from 1 to 0.25, as illustrated in table I, where each step alters the admittance by 20%, an extra ten bits or control lines would be needed. While a broader sensitivity range for adjusting the PVT output impedance is beneficial, the number of bits needed to achieve a substantial range of sensitivity using a pure thermometer code becomes excessive due to the increased design complexity and the additional chip area required for its implementation. One alternative to the issues associated with a pure thermometer code is the use of a pure binary weighted code. In this approach, each leg of the PVT control circuit consists of a resistive device with an admittance that corresponds to its specific binary weighted bit position. In other words, each leg has an admittance of 2^{(bit position)} Y, where Y is a predefined minimum admittance suited to the design. According to the binary weighted code, if bit 0 of the calibration word controls a FET with admittance Y, bit 1 controls a FET with admittance 2*Y, bit 2 controls a FET with admittance 4*Y, and so forth. In effect, as the calibration word’s binary count increases, additional resistors are added in parallel to the driver FET array, causing the output impedance (Z) to decrease. Table II provides an example of a binary weighted code. Table II demonstrates the advantage of employing a binary weighted code in its ability to achieve a wider range of output impedance with fewer bits (or PVT control lines). However, in a pure binary weighted code, a step-wise increment does not guarantee that all the legs that are activated will stay activated in the subsequent step. For instance, consider the current binary weighted calibration code as 0111 (representing an admittance of 0.7), and the code needs to be incremented to 1000 (corresponding to an admittance of 0.8). When the electrical connections switch from 0111 to 1000, it is possible that for a brief moment, the switches may be in a state where all the FETs are either turned off or turned on (corresponding to a PVT code of 1111 or 0000, respectively). This can cause an undesirable spike in the output impedance seen on the signal pad. In this case, as shown in table II, the output impedance might momentarily shift from Z=1.429 (admittance of 0.7) to Z=0.667 (admittance of 1.5, all 1s), or from Z=1.429 (admittance of 0.7) to Z=infinity (admittance of ∞, all 0s). Therefore, there is a requirement for a PVT control encoding method that enables a broader output impedance range with fewer control lines, while also preventing spikes in the output impedance on the signal pads.

TABLE II 4-bit binary weighted code

W₃	W₂	W₁	W₀	Y= 1/Z	Z
0	0	0	0	0	∞
0	0	0	1	0.1	10
0	0	1	0	0.2	5
0	0	1	1	0.3	3.333
0	1	0	0	0.4	2.5
0	1	0	1	0.5	2
0	1	1	0	0.6	1.667
0	1	1	1	0.7	1.429
1	0	0	0	0.8	1.25
1	0	0	1	0.9	1.111
1	0	1	0	1.0	1
1	0	1	1	1.1	0.909
1	1	0	0	1.2	0.833
1	1	0	1	1.3	0.769
1	1	1	0	1.4	0.714
1	1	1	1	1.5	0.667

Driver design is performed at the beginning of the IO transmitter design. Driver consist of a large PMOS and NMOS transistor to drive large external capacitance. The sizing of these transistors determine the current driving capability of the output buffer. As drivers interact with the external world and drive the off-chip loads of pF would require a strong drive strength [2]. To achieve the necessary current strength, the driver's dimensions are increased, which makes it challenging for a single pre-driver to drive it effectively. Additionally, channel reflections necessitate proper impedance matching between the driver and the PCB channel to maintain signal integrity. To address these issues, the output driver is segmented and a driver segment compose of linear-weighted driver slices (static/ anchor legs) and binary-weighted driver slices (dynamic legs) to enable the control on its impedance through multiple pre-drivers [8]. Proposed programmable IO driver design has total 3 segments. Each segment has identical pre driver, slew rate control and driver blocks. Each segment is controlled independently using a segment enable signal. In a driver segment, there are static and dynamic legs. Static or anchor legs are always turn on (depending on data) to provide impedance close to the characteristic impedance of the transmission line, while dynamic legs are turned on in parallel with anchor legs to fine-tune the impedance to match with transmission line impedance across PVT conditions. Fig. 3 shows seven equal-size anchor legs in a driver segment. Anchor legs are thermometer coded. Dynamic legs have same structure as that in anchor legs, except that they are binary weighted. The driver slice consists of 1.8 KΩ series resistor between the pull-up/ down circuit and the PAD. Each anchor leg consisting of 3 identical driver slices making the equivalent series resistor of 600Ω. Dynamic legs are binary weighted 1(20), 2, 4 and 8 driver slices with equivalent series resistor values as 1800Ω, 900Ω, 450Ω and 225Ω respectively. Total 21 driver slices for anchor legs and 15 slices for dynamic legs in a driver segment. A driver segment of 7 anchor legs and 4 dynamic legs configured using a bit stream of 11 bits in size digital control word. Anchor legs bits form the MSB and dynamic legs bits form the LSB for this control word. An 11-bit control or configuration code, where each bit 0:10 of the word W corresponds to a specific setting that enables total effective resistance matching to the line termination impedance.

Table III illustrate the configuration details for both anchor and dynamic legs, with their equivalent resistor and drive capability values ensuring proper drive strength and impedance adjustments.

TABLE III 11-bits configuration code

W₁₀	W₉	W₈	W₇	W₆	W₅	W₄	W₃	W₂	W₁	W₀
R/3	R/3	R/3	R/3	R/3	R/3	R/3	R/8	R/4	R/2	R
3*I	3*I	3*I	3*I	3*I	3*I	3*I	8*I	4*I	2*I	I
A7	A6	A5	A4	A3	A2	A1	D4	D3	D2	D1

*A stands for Anchor leg

*D stands for Dynamic leg

*R is the series resistor of a leg

*I is the drive strength of a leg

Output driver impedance matching is accomplished by programmable enabling a combination of anchor and dynamic legs FETs arranged in parallel whose combined impedance closely matches the characteristic impedance of the transmission line. It should be understood that switching devices PFET and NFET are alternately turned on and off to generate the desired output waveform. Additionally, while both devices PFET and NFET may be off to tri-state output PAD terminal, both devices will never be on simultaneously.

The design supports dynamic enablement and disablement of series and parallel termination for a bi directional IO in all IO banks. Dynamic ODT is a feature where dynamic parallel termination is enabled only when the bi-directional IO acts as a receiver and is disabled when it acts as a driver. Similarly, dynamic series termination is enabled only when the bi-directional IO acts as a driver and is disabled when it acts as a receiver, as shown in Fig. 4. This capability is beneficial for terminating any high-performance bi-directional signal path as signal integrity is optimized depending on the direction of the data. Additionally, dynamic ODT removes the requirement for external termination resistors when paired with memory devices like DDR3 SDRAM. This simplifies board layout and lowers overall costs. Dynamic ODT ensures effective line termination and impedance matching for both read and write buses. By removing the need for external resistors, it reduces component costs, conserves board space, and simplifies routing complexity.

To support High Speed IO (HSIO) operations, several interface standards have been established. Among them, High-Speed Transceiver Logic (HSTL) and Stub Series Terminated Logic (SSTL) are commonly adopted for high performance chip and memory interfaces. When carefully integrated into a Double Data Rate (DDR) architecture, these standards can facilitate operating bandwidths up to 1 Gbps. This IOB supports LVCMOS, SSTL and HSTL I/O standards, with supplies 1.8V, 1.5V, 1.35V, 1.25V and 1.2V for various applications as shown in table IV.

TABLE IV Supported IO Standards

IO Standard	Application	Standard Support
1.8V LVCMOS	General Purpose	JESD8-7A [9]
1.5V LVCMOS	General Purpose	JESD8-11A [10]
1.2V LVCMOS	General Purpose	JESD8-12A-01 [11]
1.8 V SSTL Class I and Class II	DDR2 SDRAM	JESD8-15A [12]
1.5 V SSTL Class I and Class II	DDR3	JESD79-3F [13]
1.35 V SSTL	DDR3L	JESD79-3-1A.01 [14]
1.25 V SSTL	DDR3U	JESD79-3-2 [15]
1.2 V SSTL	RLDRAM 3, QDR-IV	-
1.8 V HSTL Class I and Class II	QDR2/2+	-
1.5 V HSTL Class I and Class II	QDR, QDR2/2+, RLDRAM3	JESD8-6 [16]
1.2 V HSTL Class I and Class II	QDR-IV, General purpose	JESD8-16A [17]

All simulations were conducted across a comprehensive range of operating conditions to ensure robust IO performance. The output and core supply voltage varies ±10% of its nominal value to account for supply noise and system fluctuations. Simulations performed across a wide industrial temperature range from -40ºC to +125ºC, ensuring proper functionality under both cold and high thermal stress conditions.

A. Programmable Drive Strength

The output buffer with adjustable drive capability is employed to meet the required output current/voltage range at given IO load. A programmable architecture comprising three driver segments. Each segments integrates seven anchor legs and four dynamic legs. Programmability of the segments and gate control signals for both anchor and dynamic legs enables scalable drive current based on performance requirements. The output high current (I_OH) represents the maximum DC current a device can source through its pull-up path while maintaining the specified high-level DC output voltage (V_OH). Similarly, the output low current (I_OL) is the maximum DC current the device can sink through its pull-down path while sustaining the defined low-level DC output voltage (V_OL). I_OHand I_OL are key indicators of output buffer’s drive strength, its ability to drive a load while maintaining stable output voltage levels. It is crucial to verify that the output buffer I_OH and I_OLcomplies with the V_OH and V_OL levels defined by the JEDEC specifications. Table V lists maximum DC current (I_DC) characteristic of IO standards.

TABLE V I_DCCharacteristics

Standard	Parameter	Condition	Min	Typ	Max
1.8V LVCMOS, 18mA	I_OH(mA)	V_OH = V_CCIO - V_OL	18.17	20.14	22.07
1.8V LVCMOS, 18mA	I_OL(mA)	V_OL = 0.45V	18.09	20.04	21.97
1.5V LVCMOS, 12mA	I_OH(mA)	V_OH = 0.75* V_CCIO	12.32	15.22	18.4
1.5V LVCMOS, 12mA	I_OL(mA)	V_OL = 0.25* V_CCIO	12.28	15.16	18.34
1.2V LVCMOS/ HSTL, 10mA	I_OH(mA)	V_OH = 0.75* V_CCIO	10.24	12.65	15.31
1.2V LVCMOS/ HSTL, 10mA	I_OL(mA)	V_OL = 0.25* V_CCIO	10.23	12.63	15.29
1.8V SSTL, 10mA	I_OH(mA)	V_OH = V_CCIO – V_OL	10.28	11.42	12.55
1.8V SSTL, 10mA	I_OL(mA)	V_OL = 0.28V	10.23	11.37	12.49
1.5V SSTL, 10mA	I_OH(mA)	V_OH = 0.8* V_CCIO	10.35	12.77	15.42
1.5V SSTL, 10mA	I_OL(mA)	V_OL = 0.2* V_CCIO	10.32	12.72	15.37
1.35V SSTL, 8mA	I_OH(mA)	V_OH = 0.8* VCCIO	8.37	10.36	12.55
1.35V SSTL, 8mA	I_OL(mA)	V_OL = 0.2* V_CCIO	8.35	10.33	12.52
1.25V SSTL, 8mA	I_OH(mA)	V_OH = 0.8* V_CCIO	8.35	10.32	12.48
1.25V SSTL, 8mA	I_OL(mA)	V_OL = 0.2* V_CCIO	8.34	10.3	12.46
1.2V SSTL, 8mA	I_OH(mA)	V_OH = 0.8* V_CCIO	8.38	10.35	12.52
1.2V SSTL, 8mA	I_OL(mA)	V_OL = 0.2* V_CCIO	8.38	10.34	12.5
1.8V HSTL, 16mA	I_OH(mA)	V_OH = V_CCIO – V_OL	16.15	17.9	19.62
1.8V HSTL, 16mA	I_OL(mA)	V_OL = 0.4V	16.08	17.81	19.52
1.5V HSTL, 16mA	I_OH(mA)	V_OH = V_CCIO – V_OL	16.06	17.81	19.53
1.5V HSTL, 16mA	I_OL(mA)	V_OL = 0.4V	16.01	17.74	19.46

For the 1.8V LVCMOS standard, the simulated results demonstrate that the minimum achievable drive strength spans a range from 2mA to 18mA. It is evident that the total drive current varies significantly with operating voltage. Higher supply voltages result in stronger drive strength due to increased Vov given by “(1)”.

When all legs in 3 segments are turned on in the SE output buffer, the driving current of 18mA (maximum) is realized for 1.8V supply. Fig. 5 illustrate the simulated output waveform of the SE IOB operating at 250MHz. The transmitter circuit is designed to support three LVCMOS IO standards operating at supply voltages of 1.8V, 1.5V, and 1.2V. For each configuration, the output drive strength is set to 10 mA, and the PADSIG signals are used to drive a capacitive load of 8 pF. The transient output waveform demonstrate a well-balanced duty cycle of approximately 50%, indicating symmetrical rise and fall behavior across all supported standards.

Fig.6 presents the output waveforms for the SSTL class I standards at 1.5V, 1.35V, 1.25V, and 1.2V voltages, all driven with an 8mA current strength. The signals are driving a 5pF capacitive load at a switching frequency of 533MHz.

The displayed waveforms highlight the voltage transitions at each standard, illustrating the variations in signal amplitude, rise and fall times, and signal quality across different voltage levels. This comparison provides insight into how each voltage level influences the performance of SSTL IO drivers, especially under high-speed operation conditions with a consistent load and drive strength.

B. Programmable series and parallel termination

To achieve critically damped waveform across all PVT corners, it is essential to match the output driver resistance to the characteristic impedance of the transmission line at the midpoint voltage level (V_CCIO/ 2). Driver segment with the equivalent resistance contributed by anchor and dynamic legs enables output resistance tuning. Table VI summarizes the characteristics series termination resistance (R_S) and parallel termination or Thevenin resistance (R_T). The reported minimum, nominal and maximum values are due to PVT variations. R_OH is the pull up resistance response in Ohms for a logic low-to-high (0 → 1) transition while R_OL is the pull up resistance response in Ohms for a logic high-to-low (1 → 0). As the output voltage deviates from V_CCIO/2 so does the driver output resistance R_S. The thevenin equivalent resistance in a 3 segment driver architecture is by configuring a driver segment to pull up and another to pull down, while the third segment remains disabled.

TABLE VI R_S and R_TCharacteristics

Mode	Parameter	Min	Typ	Max
R_S 25Ω, 1.8V	R_OH(Ω)	22.79	25.07	27.91
R_S 25Ω, 1.8V	R_OL(Ω)	22.91	25.2	28.02
R_S 25Ω, 1.5V	R_OH(Ω)	22.93	25.24	28.09
R_S 25Ω, 1.5V	R_OL(Ω)	23.01	25.33	28.17
R_S 25Ω, 1.35V	R_OH(Ω)	23.02	25.35	28.23
R_S 25Ω, 1.35V	R_OL(Ω)	23.08	25.42	28.28
R_S 25Ω, 1.25V	R_OH(Ω)	23.09	25.45	28.36
R_S 25Ω, 1.25V	R_OL(Ω)	23.14	25.5	28.38
R_S 25Ω, 1.2V	R_OH(Ω)	23.13	25.51	28.43
R_S 25Ω, 1.2V	R_OL(Ω)	23.17	25.54	28.44
R_S 50Ω, 1.8V	R_OH(Ω)	44.26	49.33	55.63
R_S 50Ω, 1.8V	R_OL(Ω)	44.52	49.62	55.89
R_S 50Ω, 1.5V	R_OH(Ω)	44.59	49.72	56.05
R_S 50Ω, 1.5V	R_OL(Ω)	44.78	49.93	56.24
R_S 50Ω, 1.35V	R_OH(Ω)	44.8	49.98	56.37
R_S 50Ω, 1.35V	R_OL(Ω)	44.94	50.13	56.48
R_S 50Ω, 1.25V	R_OH(Ω)	44.96	50.2	56.65
R_S 50Ω, 1.25V	R_OL(Ω)	45.06	50.31	56.7
R_S 50Ω, 1.2V	R_OH(Ω)	45.06	50.33	56.82
R_S 50Ω, 1.2V	R_OL(Ω)	45.14	50.41	56.83
R_T 50Ω, 1.8V	R(Ω)	45.91	51.86	59.21
R_T 50Ω, 1.5V	R(Ω)	46.28	52.29	59.67
R_T 50Ω, 1.35V	R(Ω)	46.51	52.57	60
R_T 50Ω, 1.25V	R(Ω)	46.68	52.81	60.3
R_T 50Ω, 1.2V	R(Ω)	46.79	52.95	60.48

The TX is realized using a 14nm CMOS process. The layout is shown in Fig. 7. In vertical and horizontal IO design certain sub-cells are reused. This reuse strategy simplifies layout editing by maintaining a single version for non-critical cells, while critical cells are designed with at least two versions to meet matching requirements. This approach helps ensure consistent behavior between vertical and horizontal I/O types, improving similarities in both simulation results and EMIR (Electromigration and IR drop) analysis.

The configuration bits for the series (R_S) and parallel (R_T) termination remains same for different IO standards irrespective of their associated IO supply voltages (V_CCIO). An illustrative example is provided in table VII.

TABLE VII R_S and R_TTermination Configuration Bits

Test case	Parameter name	Parameter value	Remarks
R_S 50Ω	PLEG_I <10:0>	00011110000	For 1.8V/ 1.5V/ 1.2V standards. All 3 segments are enabled
R_S 50Ω	NLEG_I <10:0>	00011110000	For 1.8V/ 1.5V/ 1.2V standards. All 3 segments are enabled
R_T 50Ω	PLEG_I <10:0>	01111110000	For 1.8V/ 1.5V/ 1.2V standards. 2 segments are enabled one for pull up and other for pull down.
R_T 50Ω	NLEG_I <10:0>	01111110000

Series termination and the programmable drive strength can not be configured simultaneously for the same driver. This is because both features rely on distinct, yet overlapping configuration bit settings, making them mutually exclusive in hardware configuration.

For reliable high-speed performance in SST IO systems, it is essential to match driver output resistance to transmission line impedance. This ensures reduced signal degradation, lower jitter, and improved noise and crosstalk performance. Most modern IO drivers meet this challenge through PVT compensation [4]. In the absence of such PVT variations, most contemporary IO drivers would still deliver satisfactory performance in high-bandwidth applications. As silicon technology advances and geometries continue to shrink, die-level PVT variations are expected to increase significantly. These variations result in identical circuits across different regions of a die exhibiting differing behaviors, including I/O drivers. To mitigate this issue is to implement a driver architecture that provides a flattened output resistance response across a range of PVT conditions. The near linear output driver in this paper accomplishes this. Based on the simulation results, it can be stated that the near-linear I/O driver architecture provides a notable improved output resistance response without substantially increasing driver output load and by flattening a driver’s output resistance response helps enhance the driver’s ability to be programmed to a known value at a fixed voltage in a varying PVT environment, hence decreasing its PVT sensitivity. The near-linear output driver design is especially beneficial in applications that demand consistent output resistance across a range of DC operating conditions.

In conclusion, designing a custom layout requires careful consideration of device specifications, design constraints, and efficient power distribution. A fully custom layout enables precise control, especially for analog circuits, by optimizing transistor placement and minimizing parasitic effects. Prioritizing critical signal routing, ensuring proper shielding, and preventing ESD and latch-up issues are essential for protecting sensitive components. Layout verification tools like DRC, LVS, and antenna checks ensure compliance with design rules, enhancing manufacturability and reliability. By addressing these factors, the design can achieve optimal performance and minimize production risks.

Author Contribution

A.P. developed and designed the single-ended transmitter circuit. M.B. carried out the layout implementation.both authors discussed the results, contributed to the manuscript writing, and reviewed the final version.

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No competing interests reported.

Design and Implementation of Output Buffer in a 14nm CMOS

Status:

Version 1

Abstract

Figures

I. INTRODUCTION

II. IO BUFFER

III. SIMULATION RESULTS

A. Programmable Drive Strength

B. Programmable series and parallel termination

IV. DISCUSSIONS AND CONCLUSIONS

Declarations

Author Contribution

REFERENCES

Additional Declarations

Status:

Version 1